Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (tsv)

ABSTRACT

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and/or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe +2 /Fe +3  redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

BACKGROUND

1. Field of the Invention

The invention relates to a process of electrolytically forming conductorstructures from highly pure copper, more specifically toelectrolytically forming conductor structures from highly pure copper inthrough-silicon vias (TSVs) when producing devices such as MEMS orsemiconductor devices. Such TSVs are useful, e.g., in integratedcircuits, in a stacked or 3D arrangement, in which the TSV provideelectrical connection between the respective layers of the device, wherethe TSV have relatively large diameter, relatively great depth and ahigh aspect ratio.

2. Description of Related Art

The demands of fabricating cheaper, smaller and lighter electronicproducts offering better performance and increased functionality arecontinuously growing. The number of electronic device on a single chipis still rapidly increasing, and the ability of 2D layouts toaccommodate these demands is being exceeded. According to industryroadmaps, integrated circuit (ID) chip size will be on the order of 30nm by 2010. Such a small chip must carry more than 100 milliontransistors, which will require more than 100,000 I/Os for the nextlevel packaging. As a result, chip and MEMS designers have turned tomultilevel interconnection, which has been referred to asthree-dimensional (3-D) stacking. 3-D wafer stacking represents a waferlevel packaging technique in which specific components, such as logic,memory, sensors, A/D converters, etc., are fabricated on separate waferplatforms and then integrated onto a single wafer-scaled package usingThrough-Silicon Vias (TSVs) to provide electrical interconnectionbetween elements of the 3-D stack. Because these devices areinterconnected in the vertical axis, the electrical signal path betweencomponents becomes shorter, which results in lower parasitic losses,lower power consumption, and better system performance. Fabrication ofTSVs by electrodeposition and other techniques has been reported.Although several conductive materials such as gold, polysilicon, andtin-lead (Sn-Pb) solder have been used as interconnect material, copperis the best and most preferred choice due to its higher electricalconductivity and electromigration resistance. For the purpose ofdepositing metal in deep through-holes, e.g., TSVs, electroplating isthe most widely used process.

TSVs have been used for forming electrical connections betweenrespective layers in a stacked or 3D arrangement in devices such as MEMSand semiconductor devices, but have suffered from various defectsarising, at least partially, from difficulty in electroplating highlypure copper into the very large, high aspect ratio vias in the TSVs. Forexample, a typical TSV has an inner diameter in the range from about 1.5to about 10 microns (although greater diameter TSVs may also be used),and a depth ranging from about 5 microns to about 450 microns or evengreater depths (although wafer thicknesses of 5 to 25 microns, or of 100microns, are more common in some applications). Future inner diametersare expected to be, for example, about 1 micron. The aspect ratio(depth/width) of the typical TSV may be about 3:1 or greater, or theaspect ratio may be about 5:1, at present, or the aspect ratio may beabout 10:1, and the aspect ratio may be as high as 50:1, and futureaspect ratios are expected to be commonly from about 10:1 to about 20:1.Attempts to electrodeposit high purity copper into such high aspectratio TSVs have been partially successful, but have been plagued withproblems arising from (a) internal stresses in the copper deposit whichcan result in wafer bending or deformation upon subsequent heating, (b)non-uniform deposits (i.e., grain boundaries, crystal structure defects,etc.), (c) inclusions of gases (voids) and/or electroplating bath liquidin the body of the electrodeposited copper, which can result in waferbending and even explosive release of vapors, and (d) excess metaldeposition at the inlet and outlet of the TSV through-hole.

Of these problems, the internal stress problem (a) can be the mosttroublesome, since it results in bending and deformation of the siliconsubstrate through which the TSV is formed, and this can cause failure ofthe entire 3D arrangement. This failure may not occur until after theentire device has been fabricated, resulting in loss of not only thefailed silicon substrate, but of the whole device into which it has beenincorporated at the time of failure.

SUMMARY

In various of its embodiments, the present invention avoids thedisadvantages of known processes and, more particularly, maximizes theelectrodeposited filling of the TSVs with highly pure copper while atthe same time the invention minimizes stress, avoids defects such asinclusions and voids, as well as other defects which have been found inprior art TSVs.

The invention relates to a process of electrolytically forming conductorstructures from highly pure copper in through-silicon vias (TSVs) formedin silicon substrates such as silicon wafers used, e.g., insemiconductor devices. The process according to one embodiment of thepresent invention may be summarized as follows:

A process of electrodepositing high purity copper in a via in a siliconsubstrate to form a through-silicon-via (TSV), comprising:

providing a silicon substrate containing at least one via, wherein thevia includes an inner surface having an internal width dimension in therange from about 1.5 microns to about 30 microns, a depth from about 5microns to about 450 microns and a depth:width aspect ratio of at least3:1;

optionally, forming a dielectric layer on the inner surface of the via;

forming a barrier layer over the dielectric layer, or, if no dielectriclayer is present, forming the barrier layer over the inner surface ofthe via, wherein the barrier layer is formed of or comprises a materialwhich inhibits or provides an ability to the barrier layer to inhibitdiffusion of copper into the silicon substrate;

forming over the barrier layer a basic metal layer of sufficientthickness and coverage of the inner surface of the via to obtainsufficient conductance for subsequent electrolytic deposition of copper;

immersing the silicon substrate into an electrolytic bath in anelectrolytic copper plating system with the basic metal layer connectedas a cathode, the system further comprising an insoluble dimensionallystable anode and a source of copper metal, wherein the electrolytic bathcomprises an acid, a source of copper ions, a source of ferrous and/orferric ions, and at least one additive for controllingphysical-mechanical properties of deposited copper; and

applying an electrical voltage between the insoluble dimensionallystable anode and the basic metal layer, so that a current flowstherebetween for a time sufficient to electrodeposit high purity copperto form a TSV, wherein a Fe⁺²/Fe⁺³ redox system is established in thebath to provide additional copper ions to be electrodeposited bydissolving copper ions from the source of copper metal.

In one embodiment, the applying is effective to electrodeposit the highpurity copper to completely fill the via, with no voids and no defectsthat inhibit its function in the finished device. In another embodiment,the applying is effective to electrodeposit the high purity copper toform a copper lining in the via of sufficient thickness to be capable offunction as a TSV.

In one embodiment, the deposited high purity copper is eithersubstantially free of internal stress or includes a level of internalstress that does not result in bending of the silicon substrate uponsubsequent processing.

In one embodiment, the deposited copper is substantially free of voidsand non-copper inclusions.

In one embodiment, the basic metal layer is formed over the barrierlayer by one or more of an electroless plating process, a physicaldeposition process, a chemical vapor deposition process, or aplasma-enhanced chemical vapor deposition process.

In one embodiment, the basic metal layer has a thickness in the rangefrom about 0.02 μm to about 0.5 μm.

In one embodiment, the basic metal layer comprises copper.

In one embodiment, the barrier layer comprises tantalum.

In one embodiment, the dielectric layer, when present, comprises silicondioxide. In one embodiment, the barrier layer is a material which, inaddition to functioning as a barrier layer, also is a dielectricmaterial In one embodiment, in the electrolytic bath, the acid issulfuric acid at a concentration in the range from about 50 to about 350g/l, the source of copper ions is copper sulfate pentahydrate at aconcentration in the range from about 20 to about 250 g/l, the source offerrous and/or ferric ions is ferrous sulfate heptahydrate and/or ferricsulfate nonahydrate at a concentration in the range from about 1 toabout 120 g/l, and the at least one additive comprises one or more of apolymeric oxygen-containing compound, an organic sulfur compound, athiourea compound and a polymeric phenazonium compound.

In one embodiment, the electrical voltage is applied in a pulse currentor a pulse voltage.

In one embodiment, the electrical voltage is applied in a reverse pulseform with bipolar pulses.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a 3D device including asubstrate having mounted thereon two wafers including copper-filled TSVselectrodeposited by a process according to an embodiment of the presentinvention.

FIGS. 2-9 are schematic cross-sectional views of steps in a process offorming TSVs in a wafer and mounting the wafer onto a substrate to formpart of a 3D device such as that shown in FIG. 1 in accordance with anembodiment of the present invention.

FIGS. 10-12 are schematic cross-sectional views of steps in a process offorming TSVs in a wafer and mounting the wafer onto a substrate to formpart of a 3D device in accordance with another embodiment of the presentinvention.

DETAILED DESCRIPTION

As used herein, the term “high purity copper”, in reference to thecopper electrodeposited in accordance with the present invention, refersto copper having a purity of at least 99%, and in one embodiment, tocopper having a purity of at least 99.5%, and in another embodiment, tocopper having a purity of at least 99.9%, and in yet another embodiment,to copper having a purity of at least 99.99%, as determined by standardchemical/instrumental analytical methods. In one embodiment, ICP-MS(inductively coupled plasma mass spectrometry) is used for analysis ofthe copper raw material. As will be understood, the purity of the copperdeposit is primarily determined by the purity of the copper rawmaterial, in addition to the herein disclosed process and system.

As used herein, the term “physical-mechanical properties”, when appliedto an electrodeposited metal layer in accordance with the presentinvention, refers to one or more of brightness, ductility, grain size,hardness, resistivity, contact resistance and reliability performance.

Formation of TSVs

Formation of vias with smooth sidewalls in the silicon substrate is animportant step in the fabrication of a 3D device employing TSVs. Asknown, it is desirable to form a via at a high etch rate, with the viahaving smooth sidewalls, with a controllable sidewall angle and minimalmask undercut. A number of methods have been used, including wetetching, electrochemical etching, laser drilling and deep reactive ionetching (DRIE), and any one of them may be used in connection with thepresent invention. At present, it appears that DRIE is the most suitableprocess for forming TSVs having optimum features. DRIE creates almostvertical through-holes with relatively smooth surfaces at high etchrates. Thus, in one embodiment, DRIE is used to form the initial vias inwhich the TSVs are to be formed in the present invention.

TSVs may be created at various points in the manufacturing sequence—inthe frontend wafer fab (before or after FEOL processes), or in theassembly and packaging facility after BEOL (before or after bonding).When viewed this way, the integration schemes under consideration can beclassified as via-first or via-last, depending on when the vias arecreated. The size of the TSVs varies somewhat with the timing of the viaformation, since vias created at different points in the process may befor different purposes or uses. The following are exemplary sizes ofTSVs for various timings of TSV formation. In via-first before FEOL, theTSVs are relatively small, in the range from about 1 μm to about 5 μmdiameter and from about 5 μm to about 50 μm depth, with high aspectratios since these may be used for higher density interconnects. Invia-first after FEOL, the TSVs are typically somewhat larger, from about2 μm to about 20 μm diameter and from about 10 μm to about 150 μmdepths. In via-first applications, the number and density of TSVs may bevery high. In via-last applications, processing in the frontend waferfab is complete, and the vias generally penetrate the full stack of BEOLinsulators and conductors in addition to the silicon substrate. Invia-last before bonding, the largest TSVs are created, having diametersfrom about 5 μm to about 50 μm and depths from about 20 μm to about 400μm. The interconnect density may be lower than for via-firstapplications, and may be, e.g., on the order of one hundred TSVs perdie. Finally, in via-last after bonding, the TSVs may be smaller thanvia-last before bonding, but still may be larger than via-first, and mayhave a diameter in the range from about 2 to about 50 μm and a depth inthe range from about 10 to about 150 μm. The foregoing diameters anddepths are approximate and exemplary only, and are likely to changesignificantly in the future. The density of the TSVs for use in via-lastafter bonding may be about a hundred per die or higher. The via-lastafter bonding TSVs may be etched from the backside of a wafer that hasalready been thinned.

The sequence and timing of TSV formation and filling can be summarizedas shown in the following table:

Process Steps Via-First Etch Fill FEOL + Thinning Bonding Before BEOLadd carrier FEOL Via-First FEOL Etch Fill BEOL Bonding After FEOLThinning Via-Last FEOL + Etch Fill Thinning Bonding Before Bond BEOL addcarrier Via-Last FEOL + Bonding Thinning Etch Fill After Bond BEOL

In accordance with one embodiment of the present invention, in theprocess sequences shown in this table, the “fill” step includes aprocess of filling the TSVs by electrodeposition using a redox systembased on iron ions, as described in more detail in the following.

Filling TSVs by Electrodeposition

Complete, void-free and inclusion-free filling of TSVs with high puritycopper is a very important step in the manufacture of devicesincorporating TSVs. Incomplete metal filling, e.g., filing includingvoid formation or inclusion formation, in the TSVs can lead toshort-circuiting and will affect the electrical performance of theoverall device. Grain size of the deposited copper is very important,since grain roughness can directly affect the electrical properties suchas electrical resistivity, electromigration resistance, and internalstress in the TSV. As noted herein, the internal stress in the TSV canresult in severe problems if it causes bending or deformation of thewafer or silicon substrate through which the TSV is formed. The stresscan result from, e.g., rough grains or other defects, and the resultingdeformation or bending can cause mechanical failure of the overalldevice. Thus, obtaining smooth, void-free, inclusion-free, fine grainmetal deposition in the high aspect ratio TSVs is essential. The presentinvention provides such deposits of high purity copper.

Thus, according to the invention, a process of producing a highly purecopper fill in through-silicon vias (TSVs) formed, e.g., throughsemiconductor substrates (wafers), is provided and may be carried out.

The process, according to one embodiment of the invention, provides forelectrodepositing high purity copper in a via in a silicon substrate toform a through-silicon-via (TSV), including the following steps (1)-(6),(noting that step (2) is optional, as described below):

(1) providing a silicon substrate containing at least one via, whereinthe via includes an inner surface having an internal width dimension inthe range from about 1.5 microns to about 30 microns, a depth from about5 microns to about 450 microns and a depth:width aspect ratio of atleast 3:1;

(2) optionally, forming a dielectric layer on the inner surface of thevia;

(3) forming a barrier layer over the dielectric layer when present, orover the inner surface of the via, wherein the barrier layer is orcomprises a material which inhibits diffusion of copper into the siliconsubstrate;

(4) forming over the barrier layer a basic metal layer of sufficientthickness and coverage of the inner surface of the via to obtainsufficient conductance for subsequent electrolytic deposition of copper;

(5) immersing the silicon substrate into an electrolytic bath in anelectrolytic copper plating system with the basic metal layer connectedas a cathode, the system further comprising an insoluble dimensionallystable anode and a source of copper metal, wherein the electrolytic bathcomprises an acid, a source of copper ions, a source of ferrous and/orferric ions, and at least one additive for controllingphysical-mechanical properties of deposited copper; and

(6) applying an electrical voltage between the insoluble dimensionallystable anode and the basic metal layer, so that a current flowstherebetween for a time sufficient to electrodeposit high purity copperto form a TSV, wherein a Fe⁺²/Fe⁺³ redox system is established in thebath to provide additional copper ions to be electrodeposited bydissolving copper ions from the source of copper metal.

In one embodiment, in step (1) of the process, the silicon substrate isprovided with vias already formed. As noted above, the vias may beformed by any appropriate method, and are most often formed by reactiveion etching. At the point in the process at which the silicon substrateis provided, there may be hundreds or even thousands of vias alreadyformed. This of course depends on what point in the process of vias areto be filled, and on other factors that will be readily recognized, suchas the type of substrate, the application for which the substrate is tobe used, etc. In general, the inner surface of the via will be formed ofthe silicon of the silicon substrate or, it may be formed of a reactionproduct resulting from the reactive ion etching. Thus for example, wherethe reactive ion etching has been carried out with a halogen presentsuch as fluoride, the inner surface of the via may contain or consist ofa silicon halide, such as silicon hexafluoride. Similarly, where thereactive ion etching has been carried out with oxygen present, the innersurface of the amount contain or consist of silicon dioxide. Thus, insuch an embodiment, it would not be necessary to form a dielectric layerprior to proceeding with the subsequent steps of the process.

In one embodiment, the barrier layer is formed of a material, such assilicon nitride, which functions both as a barrier as described, and asa dielectric, in which case a separate dielectric layer need not beprovided, and the step (2) above can be omitted. Of course, even whenthe barrier layer is or functions as a dielectric, it may be desirableto form a separate dielectric layer. In some embodiments, depending onthe method by which the vias are formed, the vias may be formed with adielectric layer in place. For example, when a gas is present in the viaformation step which, when reacted with silicon, forms a dielectricsilicon compound, the via may be formed with the dielectric layer inplace.

In one embodiment, the step of applying is effective to electrodepositthe high purity copper to completely fill the via. Thus, in thisembodiment, the step of applying an electrical voltage between theinsoluble dimensionally stable anode and the basic metal layer, so thata current flows therebetween is carried out for a time sufficient toelectrodeposit high purity copper to completely fill the via and to forma TSV having no inner cavity.

In one embodiment, the step of applying is effective to electrodepositthe high purity copper to form a copper lining in the via of sufficientthickness to be capable of function as a TSV. Thus, in this embodiment,the step of applying an electrical voltage between the insolubledimensionally stable anode and the basic metal layer, so that a currentflows therebetween is carried out only for a time sufficient toelectrodeposit high purity copper to line the via with a layer of highpurity copper sufficient to provide the needed conductance. In thisembodiment, a TSV is formed having an inner cavity of whatever sizeremains after the via has been electroplated with sufficient copper.

In one embodiment, the deposited high purity copper is eithersubstantially free of internal stress or includes a level of internalstress that does not result in bending of the silicon substrate uponsubsequent processing. The presence of internal stress in the depositedhigh purity copper can result in bending or deformation of the substrateupon heating during subsequent process steps. Generally it is desirablethat the high purity copper deposit be substantially free of internalstress. Since it may not be possible to completely avoid the presence ofall internal stress, as long as the level of internal stress is lowenough that there is no bending or deformation of the substrate duringsubsequent processing, then the level of stress is acceptable.

In one embodiment, the deposited copper is substantially free of voidsand non-copper inclusions. It is very desirable that the deposited highpurity copper be free of voids and non-copper inclusions. If voids arepresent, upon subsequent heating, the voids can cause deformation or, insome cases, can result in an explosive release of gas pressure. Both thedeformation and the explosive release would result in an unsatisfactorysituation. Any non-copper inclusions that might be present would resultin a change in the conductivity of the copper, and would thereforeinterfere with the function of the TSV. For these reasons the highpurity copper deposit should not include any substantial amount ofnon-copper inclusions.

In one embodiment, the basic metal layer is formed over the barrierlayer by one or more of an electroless plating process, a physicaldeposition process, a chemical vapor deposition process, or aplasma-enhanced chemical vapor deposition process. The basic metal layeris applied to the surface of the via in order to provide a suitableconductive surface for the electrodeposition of the high purity copper.Thus it is very desirable that the basic metal layer be applied in amanner such that it will completely cover the inner surface of the via.For this reason, the chemical vapor deposition process and the plasmaenhanced chemical vapor deposition process may be more preferred than aphysical deposition process such as sputtering or an electroless platingprocess. However, both the physical deposition process and theelectroless plating process are both suitable for use when properlyapplied, as will be understood.

The basic metal layer only needs to be thick enough to provide aconductive surface onto which the copper can be electrodeposited in thesubsequent step. This thickness could be as low as a few nanometers,e.g., from about one to about 10 nm. However, in order to assure that asufficient coverage has been obtained it may be desirable to apply asomewhat thicker layer of the basic metal. Thus, in one embodiment, thebasic metal layer has a thickness in the range from about 0.01 micron toabout 0.5 micron (about 10 nm to about 500 nm). In another embodiment,the basic metal layer has a thickness in the range from about 0.02micron to about 0.25 micron, and in another embodiment the basic metallayer has a thickness in the range from about 0.05 micron to about 0.2micron.

In one embodiment, the basic metal layer comprises copper. In anotherembodiment, the basic metal layer comprises high purity copper, in whichthe copper as substantially the same purity as the later depositedcopper used to fill the via. The basic metal layer may comprise metalsother than copper, on the condition that the metal provide sufficientcoverage to the inner wall of the via and that it provide sufficientconductivity for the electrodeposited copper to adhere. Thus, forexample, in various embodiments, the metals other than copper mayinclude gold, silver, platinum, palladium, aluminum, or any of thetransition metals. However, for reasons that will be readily apparent tothe person of skill in the art, copper would be the most preferred metalfor use in the basic metal layer.

As noted above, a barrier layer is formed in the via. The barrier layeris needed to prevent diffusion of the high purity copper of the TSV intothe silicon of the substrate in which the TSV is located. The barrierlayer may be made of any material that provides a sufficient barrier todiffusion of copper into the substrate. The barrier layer may becomprised of any appropriate materials that prevent diffusion of copperatoms into the substrate, or that enable the barrier layer as a whole toinhibit such diffusion. For example, the barrier layer may be comprisedof one or more layers including materials, such as tantalum, tantalumnitride, titanium, titanium nitride and/or other suitable materials.Thus, the barrier layer is or comprises a material which inhibits thediffusion of copper into the substrate in which the TSV is formed, orthe barrier layer contains a material or sub-layer which inhibits suchdiffusion of copper. In one embodiment, the barrier layer comprisestantalum. In one embodiment the barrier layer may be formed of amaterial such as silicon nitride or silicon carbide or a silicon carbidenitride. Typically, the barrier layer may be formed by advancedwell-established sputter deposition techniques or by atomic layerdeposition (ALD), depending on the device and process requirements.

In one embodiment, the dielectric layer is present and comprises silicondioxide. In one embodiment, the dielectric layer is present andcomprises silicon nitride. In this embodiment, the silicon nitride mayprovide dual duty, by forming both a barrier to copper migration and adielectric layer to prevent current leakage. In such case, as noted, thebarrier layer can function both as barrier and as dielectric to provideelectrical insulation as well as a barrier to migration of the copper(or other metal used to fill the via).

Besides containing at least one copper ion source, preferably a coppersalt with an inorganic or organic anion, for example copper sulfate,copper methane sulfonate, copper pyrophosphate, copper fluoroborate orcopper sulfamate, the bath used for the copper deposition additionallycontains at least one substance for increasing the electricalconductance of the bath, for example sulfuric acid, methane sulfonicacid, pyrophosphoric acid, fluoroboric acid or amidosulfuric acid.

In one embodiment, in the electrolytic bath:

the acid is concentrated sulfuric acid at a bath concentration in therange from about 50 to about 350 g/l, or from about 180 g/l to about 280g/l, or from about 100 g/l to about 250 g/l, or from about 50 g/l toabout 90 g/l, the source of copper ions is copper sulfate pentahydrate(CuSO₄.5 H₂O) at a bath concentration in the range from about 20 g/l toabout 250 g/l, or from about 80 g/l to about 140 g/l, or from about 180g/l to about 220 g/l.

the source of ferrous and/or ferric ions is ferrous sulfate heptahydrateand/or ferric sulfate nonahydrate at a bath concentration in the rangefrom about 1 to about 120 g/l, or from about 1 g/l to about 20 g/l, and

the at least one additive comprises one or more of a polymericoxygen-containing compound, an organic sulfur compound, a thioureacompound or a polymeric phenazonium compound.

Further details regarding the bath and the process are provided asfollows.

The electroplating bath according to the invention contains at least oneadditive compound for controlling the physical-mechanical properties ofthe copper layers. Suitable additive compounds are, for example,polymeric oxygen-containing compounds, organic sulfur compounds,thiourea compounds, polymeric phenazonium compounds and polymericnitrogen compounds, and mixtures or combinations of any two or more ofany of these additive compounds.

Suitable, exemplary, polymeric oxygen-containing compounds include oneor more of the following:

carboxymethyl cellulose

nonylphenol-polyglycol ether

octanediol-bis-(polyalkyleneglycol ether)

octanolpolyalkyleneglycol ether

oleic acid polyglycol ester

polyethylene-propyleneglycol copolymer

polyethyleneglycol

polyethyleneglycol-dimethylether

polyoxypropyleneglycol

polypropyleneglycol

polyvinyl alcohol

stearic acid polyglycol ester

stearyl alcohol polyglycol ether

β-naphtol polyglycol ether.

The polymeric oxygen-containing compounds additive compounds may becontained in the electrodeposition bath at a concentration in the rangefrom about 0.005 g/l to about 20 g/l, and in one embodiment, from about0.01 g/l to about 5 g/l.

Suitable, exemplary sulfur compounds with suitable functional groups forproviding water solubility include one or more of the following:

-   -   3-(benzothiazolyl-2-thio)-propylsulfonic acid, sodium salt    -   3-mercaptopropane-1-sulfonic acid, sodium salt    -   ethylenedithiodipropylsulfonic acid, sodium salt    -   bis-(p-sulfophenyl)-disulfide, disodium salt    -   bis-(ω-sulfobutyl)-disulfide, disodium salt    -   bis-(ω-sulfohydroxypropyl)-disulfide, disodium salt    -   bis-(ω-sulfopropyl)-disulfide, disodium salt    -   bis-(ω-sulfopropyl)-sulfide, disodium salt    -   methyl-(ω-sulfopropyl)-disulfide, disodium salt    -   methyl-(ω-sulfopropyl)-trisulfide, disodium salt    -   O-ethyl-dithiocarboxylic acid-S-(ω-sulfopropyl)-ester, potassium        salt thioglycolic acid    -   thiophosphoric acid-O-ethyl-bis-(ω-sulfopropyl)-ester, disodium        salt    -   thiophosphoric acid-tris-(ω-sulfopropyl)-ester, trisodium salt.        The water-soluble organic sulfur additive compounds may be        contained in the electrodeposition bath at a concentration in        the range from about 0.0005 g/l to about 0.4 g/l, and in one        embodiment, from about 0.001 g/l to about 0.15 g/l.

Suitable, exemplary thiourea-type compounds include one or more of thefollowing:

-   -   thiourea    -   N-acetylthiourea    -   N-trifluoroacetylthiourea    -   N-ethylthiourea    -   N-cyanoacetylthiourea    -   N-allylthiourea    -   o-tolylthiourea    -   N,N′-butylene thiourea    -   thiazolidine thiol    -   4-thiazoline thiol    -   imidazolidine thiol (N,N′-ethylene thiourea)    -   4-methyl-2-pyrimidine thiol    -   2-thiouracil.

Suitable, exemplary phenazonium compounds include one or more of thefollowing:

-   -   poly(6-methyl-7-dimethylamino-5-phenyl phenazonium sulfate)    -   poly(2-methyl-7-diethylamino-5-phenyl phenazonium chloride)    -   poly(2-methyl-7-dimethylamino-5-phenyl phenazonium sulfate)    -   poly(5-methyl-7-dimethylamino phenazonium acetate)    -   poly(2-methyl-7-anilino-5-phenyl phenazonium sulfate)    -   poly(2-methyl-7-dimethylamino phenazonium sulfate)    -   poly(7-methylamino-5-phenyl phenazonium acetate)    -   poly(7-ethylamino-2,5-diphenyl phenazonium chloride)    -   poly(2,8-dimethyl-7-diethylamino-5-p-tolyl-phenazonium chloride)    -   poly(2,5,8-triphenyl-7-dimethylamino phenazonium sulfate)    -   poly(2,8-dimethyl-7-amino-5-phenyl phenazonium sulfate)    -   poly(7-dimethylamino-5-phenyl phenazonium chloride).

Suitable, exemplary polymeric nitrogen-containing compounds include oneor more of the following:

-   -   polyethylenimine    -   polyethylenimide    -   polyacrylic acid amide    -   polypropylenimine    -   polybutylenimine    -   N-methylpolyethylenimine    -   N-acetylpolyethylenimine    -   N-butylpolyethylenimine.

The thiourea-type compounds, polymeric phenazonium compounds andpolymeric nitrogen containing compounds, as the additive compounds, maybe used at a concentration in the range from about 0.0001 g/l to about0.50 g/l, and in one embodiment, from about 0.0005 g/l to about 0.04g/l.

As noted above, in order to achieve the effects, according to theinvention, when using the claimed process, Fe(II) and/or Fe(III)compounds are contained in the bath. Suitable iron salts are both theiron(II)-sulfate-heptahydrate and iron(III)-sulfate-nonahydrate, fromeither or both of which the effective Fe²⁺/Fe³⁺ (Fe(III)/Fe(III)) redoxsystem is formed after a short operational time. These salts are mainlysuitable for aqueous, acidic copper baths. Other water-soluble ironsalts may also be used, for example iron perchlorate. Salts whichcontain no (hard) complex formers are advantageous. Such complex formersmay be biologically non-degradable or only may be degradable with somedifficulty, thus such salts may create problems when disposingoff-rinsing water (for example iron ammonium alum). Iron compoundshaving anions which lead to undesirable secondary reactions in the caseof the copper deposition solution, such as chloride or nitrate forexample, should not be used, if possible. In consequence, carboxylatesof iron ions, such as acetate, propionate and benzoate, as well as thehexafluorosilicates, are also advantageous. Suitable systems employingthe Fe²⁺/Fe³⁺ redox system are disclosed, for example, in U.S. Pat. Nos.5,976,341 and 6,099,711, which may be consulted for additional detailson this system. The disclosures of both of these U.S. patents relatingto the use the Fe²⁺/Fe³⁺ redox system are incorporated herein byreference.

The concentration of the iron ion substance(s) may be as follows. In oneembodiment, the iron ions are added as iron(II)-sulfate (FeSO₄.7H₂O) ata concentration in the range from about 1 g/l to about 120 g/l, and inone embodiment from about 20 g/l to about 80 g/l. In one embodiment, thebath is prepared to initially contain from about 1 g/l to about 30 g/lferrous ions (based on actual Fe content, added as, e.g., ferroussulfate heptahydrate) and from about 1 g/l to about 30 g/l ferric ions,in one embodiment, from about 2 to about 10 g/l, and in anotherembodiment, from about 3 to about 5 g/l (based on actual Fe³⁺ content,added as, e.g., ferric sulfate nonahydrate). In one embodiment, the bathis prepared to initially contain from about 2 g/l to about 20 g/lferrous ions (based on actual Fe²⁺ content, added as, e.g., ferroussulfate heptahydrate) and from 4 g/l to about 20 g/l ferric ions (basedon actual Fe³⁺ content, added as, e.g., ferric sulfate nonahydrate). Inone embodiment, the bath is prepared to initially contain from about 3g/l to about 10 g/l ferrous ions (based on actual Fe²⁺ content, addedas, e.g., ferrous sulfate heptahydrate) and from 5 g/l to about 20 g/lferric ions (based on actual Fe³⁺ content, added as, e.g., ferricsulfate nonahydrate). As will be recognized, since there is a continuouscycling of the ferrous and ferric ions in the redox system, the actualconcentrations of both ions may vary from the initial concentrations.

Since the copper ions consumed during the deposition from the depositionsolution cannot be directly supplied by the anodes by dissolution wheninsoluble anodes are used, these copper ions are supplemented bychemically dissolving corresponding copper parts or copper-containingshaped bodies. In the redox system, copper ions are formed from thecopper parts or shaped bodies in a redox reaction by the oxidizingeffect of the Fe(III) compounds contained in the deposition solution, inwhich the Fe(III) ions are reduced to Fe(II) ions by the copper metalbeing oxidized to form Cu(II) ions in the electroplating bath, asdescribed above. By means of this formation of the copper ions, thetotal concentration of the copper ions contained in the depositionsolution is kept relatively constant, and the anodes remain the sameuniform size. The deposition solution passes from the copper iongenerator back again into the electrolyte chamber which is in contactwith the wafers and the anodes. As will be recognized, the followingreactions take place:

At the anodes:

Fe²⁺→Fe³⁺+e⁻

At the copper source:

Cu⁰+2 Fe³⁺→Cu²⁺+2 Fe²⁺

At the cathode (e.g., at the semiconductor substrate):

Cu²⁺+2 e⁼→Cu⁰ (main reaction)

Fe³⁺+e⁻→Fe²⁺(minor reaction)

Thus, the system may be initialized with either or both a source offerrous ion or a source of ferric ion, since the redox reactioninterconverts these ions as the process proceeds. In one embodiment, thesystem is initialized with both a source of ferrous ions and a source offerric ions. As a result of this process, the concentration of thecopper ions in the deposition solution can be kept constant very easily,which helps to maintain uniformity of the copper deposit.

In one embodiment, the electrodeposition bath is substantially free ofan added chloride, for example sodium chloride or hydrochloric acid.Chlorides have been used in similar electroplating baths, but inaccordance with this embodiment of the present invention, the chlorideis omitted. As used herein, when a possible bath component is omittedfrom the bath, or when a bath is referred to as being “free of” acomponent, this means that none of the component is intentionally addedto the bath. Small amounts of such components may be present asimpurities, but they are not added intentionally.

For the electrolytic copper deposition of the present invention, avoltage is applied between the semiconductor substrate and the anode,the voltage being so selected that an electric current of 0.05 amps perdm² (A/dm²) to 20 A/dm², in one embodiment, 0.2 A/dm² to 10 A/dm² and,in another embodiment, 0.5 A/dm² to 5 A/dm², where the current flows areexpressed as amps per dm² of, e.g., semiconductor substrate surface,assuming that the plating is applied to the entire surface of thesubstrate.

In one embodiment, a pulse current or pulse voltage method is used. Inthe pulse current method, the current between the workpieces, polarizedas the cathode, and the anodes, is set galvanostatically and modulatedper unit time by suitable means. In the pulse voltage method, a voltagebetween the wafers, as cathodes, and the counter-electrodes, as anodes,is set potentiostatically, and the voltage is modulated per unit time sothat a current is set which is variable per unit time.

The method, which is known as the reverse pulse method, in oneembodiment is used with bipolar pulses. Those methods are especiallysuitable, in which the bipolar pulses comprise a sequence of cathodicpulses, lasting from 20 milliseconds to 100 milliseconds, and anodicpulses lasting from 0.3 milliseconds to 10 milliseconds. In oneembodiment, the peak current of the anodic pulses is set to at least thesame value as the peak current of the cathodic pulses. In oneembodiment, the peak current of the anodic pulses is set two to threetimes as high as the peak current of the cathodic pulses.

In one embodiment, the electrical voltage is applied in a pulse currentor a pulse voltage. In one embodiment, the electrical voltage is appliedin a reverse pulse form with bipolar pulses. These processes are wellknown in the art, and detailed parameters for use with some embodimentsof the present invention are described in more detail in the following.

In one embodiment, the electrical voltage is applied in a reverse pulseform with bipolar pulses including a forward current pulse and a reversecurrent pulse. In one embodiment, the duration of the reverse currentpulse is adjusted to about 1 to about 20 milliseconds, and in anotherembodiment, the duration of the reverse current pulse is adjusted toabout 2 to about 10 milliseconds. In one embodiment, the duration of theforward current pulse is adjusted to about 10 to about 200 milliseconds,and in another embodiment, the duration of the forward current pulse isadjusted to about 20 to about 100 milliseconds.

In one embodiment, peak current density of the forward current pulse ata work piece surface is adjusted to a maximum of about 15 amps persquare decimeter (A/dm²), and in another embodiment, peak currentdensity of the forward current pulse at a work piece surface is adjustedto a maximum of about 1.5 to about 8 A/dm². In one embodiment, the peakcurrent density of the reverse current pulse at a work piece surface isadjusted to a maximum of about 60 A/dm², and in another embodiment, peakcurrent density of the reverse current pulse at a work piece surface isadjusted to a maximum of about 30 to about 50 A/dm².

In one embodiment, a first current pulse is shifted with respect to asecond current pulse by about 180°. A pause of suitable duration may beincluded between the first current pulse and the second current pulse. Asuitable duration may range, for example, from about 1 millisecond toabout 5 milliseconds, and in one embodiment is from about 2 millisecondsto about 4 milliseconds, and in one embodiment, is about 4 milliseconds.

In one embodiment, when compared to a copper electrodeposition system inwhich the redox system of the present invention is not used or notpresent, the redox system according to the present invention exhibitsreduced consumption of organic additives. This unexpected benefit isbelieved to result from reduced oxidation of the organic additives atthe anodes. In one embodiment, when compared to a copperelectrodeposition system in which the redox system is not used orpresent, the redox system according to the present invention consumesonly about 30% of the organic additives that would be consumed by thenon-redox system.

In one embodiment, no soluble anodes made of copper are used as theanodes; rather, dimensionally stable, insoluble anodes are used. Byusing the dimensionally stable, insoluble anodes, a constant spacing canbe set between the anodes and the wafers. The anodes are easilyadaptable to the wafers in respect of their geometrical shape and,contrary to soluble anodes, they substantially do not change theirgeometrical external dimensions. In consequence, the spacing between theanodes and the wafers, which can influence the distribution of layerthickness on the surface of the wafers, remains constant. Without suchconstant spacing, variations in layer thickness and quality may result,causing non-uniform copper deposits.

To produce insoluble anodes, (inert) materials which are resistant tothe electrolyte are used, such as stainless steel or lead for example.Anodes may be used which contain titanium or tantalum as the basicmaterial, which may be coated with noble metals or oxides of the noblemetals. Platinum, iridium or ruthenium, as well as the oxides or mixedoxides of these metals, may be used, for example, as the anode coating.Besides platinum, iridium and ruthenium, rhodium, palladium, osmium,silver and gold, or respectively the oxides and mixed oxides thereof,may also be used for the anode coating. A particularly high resistanceto the electrolysis conditions may be obtained, for example, on atitanium anode having an iridium oxide surface, which was irradiatedwith fine particles, spherical bodies for example, and therebycompressed in a pore-free manner. In one embodiment, anodes may be usedwhich are formed from noble metals, for example platinum, gold orrhodium or alloys of these metals. Other inert, electrically conductivematerials, such as carbon (graphite), may also be used.

In one embodiment, the wafers are processed in a horizontal orientationfor the copper deposition. Anodes in the deposition bath, also kepthorizontal, are disposed directly opposite the wafers. Sincedimensionally stable insoluble electrodes are employed, the distancebetween the anodes and the cathodic parts of the wafer or semiconductordevice is maintained substantially constant.

The process according to the invention is especially suitable forfilling vias to form TSVs in silicon substrates in, e.g., semiconductordevices, silicon wafers and MEMS devices.

In one embodiment, a dielectric layer is formed on the inner surface ofthe vias, during or subsequent to the step of etching to form theinitial vias. The oxidation of silicon results in the formation ofsilicon dioxide, and this dielectric material may be employed to provideelectrical isolation of the TSVs from the surrounding silicon substrate,chip or wafer. The dielectric layer may be formed by any suitableprocess. In another embodiment, a silicon dioxide layer is formed, forexample, by a TEOS process or by an oxidation of the silicon sidewallsof the via. Suitable methods for formation of a layer of such dielectricmaterials are known in the art and may be selected by the person ofskill in the art as needed.

Since the TSVs will be filled with high purity copper in accordance withthe present invention, suitable measures should be taken to prevent thediffusion of copper atoms into the silicon substrate situated adjacentto the TSVs. Thus, in one embodiment, a barrier layer is formed on theinner sidewalls of the TSV, in order to provide a barrier to diffusionof the later-deposited copper into the silicon of the substrate throughwhich the TSV is formed. In one embodiment, the barrier layer is atantalum-containing material capable of reducing and/or eliminatingdiffusion of copper therethrough. In one embodiment, in order to producea diffusion barrier between the copper layer and the silicon substrate,therefore, a nitride layer (tantalum nitride layer for example) isformed, for example, by a sputtering process. Suitable methods forformation of a layer of such barrier materials are known in the art andmay be selected by the person of skill in the art as needed.

In order to permit the copper to be electrolytically deposited on thedielectric surface of the barrier layer, the barrier layer may be madeelectrically conductive by deposition of a suitable base metal layerover the barrier layer. In one embodiment, the base metal layer issubsequently applied, which forms an electrically conductive base forthe subsequent electrolytic metallization. In one embodiment, afull-surface layer having a thickness in the range from about 0.02 μm toabout 0.3 μm, is applied as the basic metal layer. In one embodiment,the base metal layer is applied by a physical metal deposition processand/or by a CVD process and/or by a PECVD process. In addition oralternatively, a plating process may also be used, for example anelectroless metal deposition process. For example, a basic metal layerformed from copper may be deposited. Other conductive layers, usuallymetal layers, may also be suitable. Such conductive layers may include,for example, a metal such as tungsten, silver, gold, platinum, zinc, tinor any other metal or silicide known for use as a seed layer forelectrodeposition of copper onto a non-conductive substrate.

After the base metal layer has been formed, the copper fill for the TSVis electrolytically deposited according to the above-described process.

In one embodiment, the process of the present invention is integratedinto a semiconductor fabrication process, and includes

lithography and masking for the etch process,

DRIE or laser etching for creation of the TSV,

formation of a dielectric isolation layer by an oxidation,

formation of a barrier layer by physical vapor deposition, thermaland/or CVD,

formation of a base metal or seed layer by an appropriate method, suchas a copper electroless process,

copper electrodeposition filling of the TSV as described in detailherein,

appropriate treatment such as CMP and cleaning, to complete formation ofthe filled TSV.

The wafer or semiconductor device may then be processed using standardtechnology, such as CMOS, and later subjected to processes such asthinning, lithography, solder bump, dicing and then die-to-die,die-to-wafer, wafer-to-wafer or other appropriate 3D construction byvarious known methods. In general, manufacturing aspects relating toTSVs may include via formation, metallization, wafer thinning,alignment, and bonding.

The following non-limiting examples are provided to illustrate anembodiment of the present invention and to facilitate understanding ofthe invention, but are not intended to limit the scope of the invention,which is defined by the claims appended hereto.

EXAMPLE 1

To produce a TSV filled with a high purity copper deposit, a wafer isprovided with vias having a diameter of about 10 microns and a depth ofabout 50 microns. The vias are initially coated with a dielectric layerof silicon dioxide formed by high temperature oxidation of the innersidewalls of the vias. The dielectric layer on the inner sidewalls ofthe vias is next coated with a diffusion barrier layer formed fromtantalum nitride applied by sputtering. Subsequently, the diffusionbarrier layer is coated with a copper base metal layer by a sputteringprocess, in which the copper base metal layer has a thickness of about0.1 micron. The wafer is then immersed in a copper deposition bathdescribed below in which the wafer is connected as a cathode and aninsoluble anode is included. The via is filled with high purity copperby electrodeposition from the bath having the following ingredients, toform the TSVs in accordance with the present invention:

H₂SO₄, 98% by wt. 130 g/l CuSO₄•5 H₂O  70 g/l FeSO₄•7 H₂O  15 g/l andpolyethylene glycol  8 g/lin water.

The high purity copper is electrodeposited under the followingconditions:

-   -   cathodic current density 4 A/dm²    -   circulation of the bath 5 l/min    -   at room temperature.

Pulsed current is applied with the parameters shown in the table below.

EXAMPLE 2

Copper stress in TSVs deposited by different plating methods using theabove-disclosed bath in accordance with the invention and either using asimilar bath without the added Fe²⁺/Fe³⁺ ions or using a similar bathbut with a soluble copper anode, in which pulsed current is applied withthe parameters shown in the table below:

Pulse in milliseconds Phase I_(forward)/I_(reverse) Forward-/ Pulse-gapin shift in Examples in A/dm² Reverse-Pulse milliseconds degrees 1 and 26/40 72/4 4 180

Electrodeposition Method Stress Soluble Copper Anode: 163.2 ± 34.3 MPa(prior art) Soluble Copper Anode w/Fe²⁺/Fe³⁺ redox 113.4 ± 40.1 MPa(prior art) Inert Anode w/Cu/Cu²⁺/Fe²⁺/Fe³⁺ redox  66.9 ± 9.8 MPa(present invention)

The internal stress is measured as deposited without a post-annealingstep. The measurement is via wafer warpage and bow (LASER measurement).The equipment used was a KLA-TENCOR FLX-2320 thin film stressmeasurement system, copper film thickness 1 micron, wafer thickness 750micron.

As is clearly shown by the data from Example 2, when TSVs are filled inaccordance with the present invention, significantly lower andsignificantly more consistent stress levels are obtained in the TSVs.

FIG. 1 is a schematic cross-sectional view of a 3D device 100 includinga substrate 102 having mounted thereon two wafers 104 and 106, includingcopper-filled TSVs 108 a, 108 b, 108 c, 110 a, 110 b and 110 c, in whichthe TSVs have been electrodeposited by a process according to anembodiment of the present invention. The substrate 102 may be anysuitable substrate, such as a chip, a wafer or some other substrate uponwhich one or more chips or wafers is to be attached to form a 3D devicesuch as the 3D device 100 depicted in FIG. 1. As shown in FIG. 1, the 3Ddevice 100 further includes solder bumps 112 a, 112 b, 112 c, 114 a, 114b and 114 c, by which the respective filled TSVs 108 a, 108 b, 108 c,110 a, 110 b and 110 c are electrically interconnected to each other andto electrical wiring 116 in the substrate 102. Finally, as shown in FIG.1, the 3D device 100 further includes under fill material 118 betweenthe wafer 104 and the substrate 102 and between the wafer 104 and thewafer 106. It is noted that FIG. 1 is a highly schematic depiction of a3D device, and for the sake of clarity and simple explanation omits thevarious functional elements that would be present in the variouselements of the 3D device, so as to more clearly depict the importantelements of the 3D device which can be formed by a process includingvarious embodiments of the present invention.

FIGS. 2-9 are schematic cross-sectional views of steps in a process offorming TSVs in a wafer and mounting the wafer onto a substrate to formpart of a 3D device such as the 3D device 100 shown in FIG. 1, inaccordance with an embodiment of the present invention. The processdepicted in FIGS. 2-9 is presented schematically and, as will beunderstood, may be carried out in the appropriate selected order asdescribed above, with respect to the “via first” or “via last”, beforeor after FEOL and before or after bonding.

FIG. 2 depicts a silicon substrate, such as a wafer, chip or othersilicon substrate which may be used, e.g., in a semiconductor device,through which TSVs are to be formed.

In the next step of a process according to an embodiment of the presentinvention, TSVs are formed in the silicon substrate 104. As disclosedabove, any suitable method of forming TSVs may be used, and in oneembodiment, the method is DRIE. This formation is indicated by the arrowleading from FIG. 2 to FIG. 3.

FIG. 3 depicts the silicon substrate of FIG. 2 after the TSVs 120 a, 120b and 120 c have been formed through most of the thickness of thesilicon substrate 104. It is noted that, for simplicity, only three TSVs120 a-120 c are depicted in FIGS. 1-8, but as disclosed above, a givenwafer or semiconductor device may contain hundreds or thousands of suchTSVs. It is further noted that, for simplicity, the TSVs 120 a-120 c inFIG. 3, and in all of the FIGS. 1 and 3-9, are shown as having vertical,parallel sidewalls; this is for purposes of ease of illustration and isnot intended to depict a required situation. As is known, while thesidewalls may be vertical or substantially vertical, in someembodiments, the sidewalls in TSVs generally taper slightly from top tobottom, i.e., from the opening of the via to the bottom of the via, sothat the diameter at the bottom is slightly smaller than the diameter atthe top opening or mouth of the via.

Subsequent to formation of the TSVs 120 a-120 c, in the next step of aprocess according to an embodiment of the present invention, on theentire inside surface of the sidewalls of each TSV 120 there optionallymay be deposited a dielectric layer 122, as shown in FIGS. 4 and 4 a.Due to the scale of FIG. 4, an expanded view of a portion of the TSV 120c and the subsequently applied layers are shown in FIGS. 4 a, 4 b and 4c. As described above, the dielectric layer 122 is provided as anelectrical insulation layer between the subsequently formed conductivefill of the TSV and the adjacent silicon substrate 104. The entire innersurface of each TSV 120 a-120 c should be covered with the dielectriclayer 122. As will be understood, the relative proportions of the layersand the substrate 104 are not to scale. As noted above, the dielectriclayer is optional, and in an appropriate embodiment, the stepillustrated in FIG. 4a can be omitted, e.g., when the barrier layersubsequently formed also functions as a dielectric.

Next a barrier layer 124 is deposited or formed over the dielectriclayer 122, as shown in FIG. 4 b. The barrier layer may be formed of amaterial such as, for example, tantalum (Ta), tantalum/tungsten (TaW) ortantalum nitride (TaN), or other material known to function as a barrierto copper migration. The barrier layer 124 is provided in order toprevent migration of copper into the adjacent silicon substrate 104. Thebarrier layer may be deposited by any appropriate method known in theart for deposition of such a layer.

Following formation of the barrier layer 124, as shown in FIG. 4 c, inthe next step of a process according to an embodiment of the presentinvention, a conductive base metal or seed layer 126 is deposited on thesurface of the barrier layer 124 lining the TSVs 120 a-120 c. Asdescribed above, the base metal layer 126 may be any appropriateconductive metal layer, and in one embodiment is copper, and in anotherembodiment is high-purity copper. The base metal layer 126 may bedeposited by any appropriate method known in the art for deposition ofsuch a layer. The base metal layer 126 provides a conductive surfaceupon which the electrodeposition of the TSV fill metal can take place.

The next step of a process according to an embodiment of the presentinvention, each of the TSVs 120 a-120 c are filled with high puritycopper by an electrodeposition process as described above, to form thefilled TSVs 108 a-108 c, as depicted in FIG. 5. The high purity copperis electrodeposited using the redox system described above, such thatthe copper is deposited on the base metal layer 126, and the high puritycopper completely fills the TSVs with essentially no voids orinclusions, in accordance with an embodiment of the present invention.

It is noted that, in FIGS. 1 and 5-9, although the dielectric layer 122,the barrier layer 124 and the conductive layer 126 are not clearly showndue to the scale of the drawings, they are deemed to be present, havingbeen formed as described above, and shown in FIGS. 4 a, 4 b and 4 c.

FIGS. 6-9 schematically depict certain steps in a process of attaching asilicon substrate 104 containing the filled TSVs 108 a-108 c to thesubstrate 102. Also, at this time, any needed removal of the variouslydeposited layers from other surfaces of the wafer may be carried out.For example, the copper electrodeposition may cover the entire uppersurface of the wafer, and may be removed, e.g., by chemical-mechanicalpolishing (CMP). Suitable methods for removing excess material depositedin the course of carrying out the processes described herein may beselected as needed by those of skill in the art. These layers and stepsfor removing them are not shown in the drawings, but will be readilyunderstood and appreciated by the skilled person.

In FIG. 6, the wafer containing the newly formed TSVs 108 a-108 c hasbeen thinned, thus exposing the lower or bottom end of the TSVs 108a-108 c to enable electrical connection of the TSVs 108 a-108 c insubsequent steps. The thinning may be carried out by any known methodfor thinning semiconductor wafers, chips, etc.

In FIG. 7, the silicon substrate 104 containing the filled TSVs 108a-108 c is positioned above or adjacent to the substrate 102. As shown,the substrate 102 includes the electrical wiring 116, similar to thatshown in FIG. 1. As shown, in FIG. 7, solder beads or balls 112 a, 112 band 112 c have been placed in locations at which the TSVs 108 a-108 cwill contact exposed portions of the electrical wiring 116. The solderbeads 112 a-112 c may be formed of any suitable material, such astin-lead solder or any other known solder material used for making suchattachments, and may be deposited according to any known method.

As depicted in FIG. 8, the next step is contacting each of the TSVs 108a-108 c to the solder beads 112 a-112 c, which are in turn in contactwith the electrical wiring 116 in the substrate 102, and thereby tocreate an electrical connection between the respective TSVs 108 a-108 cto the electrical wiring 116 via the respective solder beads 112 a-112c. The contacting may be by any known method.

As depicted in FIG. 9, the underfill material 118 a can be added to fillthe or any space remaining between the silicon substrate 104 and thesubstrate 102. In one embodiment, the underfill material is placedfollowing the step of contacting the TSVs to the solder beads, and inanother embodiment, the underfill material 118 a is applied to thesubstrate prior to the contacting. As will be understood, the underfillmaterial 118 a may be applied before or after the solder beads.

It is noted that, in an embodiment in which the TSV is formed afterbonding in a “via last” approach, the step of etching may form TSVs thatpenetrate through the entire thickness of the silicon substrate (notshown). In some such cases, a lower layer to which the wafer has alreadybeen bonded may act as an etch stop layer.

In another embodiment, in some applications in which the TSVs are verylarge, i.e., having a diameter from about 20 μm to about 50 μm, it maynot be necessary to entirely fill the TSV, but instead as long as athick lining is formed, the high conductivity of the copper may besufficient to provide the electrical conductivity required of the TSVs.

FIGS. 10-12 are schematic cross-sectional views of steps in a process offorming TSVs in a wafer and mounting the wafer onto a substrate to formpart of a 3D device in accordance with another embodiment of the presentinvention.

FIG. 10 depicts the wafer into which a TSV is being formed at a point inthe process corresponding to FIG. 4 c, after the via 220 has beenformed, a dielectric layer 222, a barrier layer 224 and a base metalconductive layer 226 have been deposited on the sidewalls in sequence asdescribed with the embodiment of FIGS. 4, 4 a, 4 b and 4 c, and in whichthe materials deposited and methods therefore are the same as have beendescribed above.

The next step of the process according to this embodiment of theinvention, in the wafer 200, each of the vias 220 are lined, but are notcompletely filled, with a relatively thick and uniform layer of highlypure copper by an electrodeposition process as described above, to formthe lined TSVs 208, as depicted in FIG. 11. The highly pure copper iselectrodeposited using the redox system described above, such that thecopper is deposited on the base metal layer 226, and the highly purecopper completely lines the inner walls of the TSVs with a thick layerof the highly pure copper. The layer of high purity copper itselfcontains essentially no voids or inclusions, in accordance with anembodiment of the present invention. The layer has a thickness which,when coupled with the relatively large size of the TSV, providesadequate conductivity without requiring the TSV 208 to be completelyfilled. Thus, in this embodiment, as schematically depicted in FIG. 11,the TSV 208 includes one large, central opening 228, in that the via 220has not been completely filled but instead is covered with a uniformlythick layer of the high purity copper by the process in accordance withthis embodiment of the invention.

Following formation of the TSV 208, the wafer 200 is then thinned toprovide the wafer at the stage shown in FIG. 12. In FIG. 12, the wafercontaining the newly formed TSVs 208 has been thinned, thus exposing thelower or bottom end of the TSVs 208 to enable electrical connection ofthe TSVs 208 in subsequent steps. The thinning may be carried out by anyknown method for thinning semiconductor wafers, chips, etc.

It is noted that in the embodiment shown in FIG. 12, the layersincluding the dielectric layer 222, the barrier layer 224, the basemetal layer 226 and the high purity copper layer 208 have not yet beenremoved from the upper surface of the wafer 200. These layers would alsobe present in the embodiment of the invention described with respect toFIGS. 2-9, but in describing that embodiment, the step of removing theselayers was not specifically described. Such step would have been carriedout subsequent to the step of electroplating with high purity copper inaccordance with the invention, and had already been completed at thepoint in the process depicted in FIG. 5. In that embodiment, and in theembodiment described with respect to FIG. 12, the copper layer cansimply be removed, e.g., by CMP, or it can be patterned to create anelectrical circuit on that surface of the wafer. In the latter case,where the patterned electrical circuit is desired, the pattern may beformed by a photoresist process prior to the step of electroplating withhigh purity copper. While it is also possible to carry out the patternformation steps subsequent to the step of electroplating with highpurity copper, it is considered to be more efficient to form thepattern, e.g., by a photoresist process, prior to the step ofelectroplating with high purity copper.

It is noted that, throughout the specification and claims, the numericallimits of the disclosed ranges and ratios may be combined, and aredeemed to include all intervening values. Thus, for example, whereranges of 1-100 and 10-50 are specifically disclosed, the ranges of1-10, 1-50, 10-100 and 50-100 are deemed to be within the scope of thedisclosure, as are the intervening integral values. Furthermore, allnumerical values are deemed to be preceded by the modifier “about”,whether or not this term is specifically stated. Finally, all possiblecombinations of disclosed elements and components are deemed to bewithin the scope of the disclosure, whether or not specificallymentioned. That is, terms such as “in one embodiment” are deemed todisclose unambiguously to the skilled person that such embodiments maybe combined with any and all other embodiments disclosed in the presentspecification.

While the principles of the invention have been explained in relation tocertain particular embodiments, and are provided for purposes ofillustration, it is to be understood that various modifications thereofwill become apparent to those skilled in the art upon reading thespecification. Therefore, it is to be understood that the inventiondisclosed herein is intended to cover such modifications as fall withinthe scope of the appended claims. The scope of the invention is limitedonly by the scope of the appended claims.

1. A process of electrodepositing high purity copper in a via in asilicon substrate to form a through-silicon-via (TSV), comprising:providing a silicon substrate containing at least one via, wherein thevia includes an inner surface having an internal width dimension in therange from about 1.5 microns to about 30 microns, a depth from about 5microns to about 450 microns and a depth:width aspect ratio of at least3:1; optionally, forming a dielectric layer on the inner surface of thevia; forming a barrier layer over the inner surface of the via or overthe dielectric layer when present, wherein the barrier layer inhibitsdiffusion of copper into the silicon substrate; forming over the barrierlayer a basic metal layer of sufficient thickness and coverage of theinner surface of the via to obtain sufficient conductance for subsequentelectrolytic deposition of copper; immersing the silicon substrate intoan electrolytic bath in an electrolytic copper plating system with thebasic metal layer connected as a cathode, the system further comprisingan insoluble dimensionally stable anode and a source of copper metal,wherein the electrolytic bath comprises an acid, a source of copperions, a source of ferrous and/or ferric ions, and at least one additivefor controlling physical-mechanical properties of deposited copper; andapplying an electrical voltage between the insoluble dimensionallystable anode and the basic metal layer, so that a current flowstherebetween for a time sufficient to electrodeposit high purity copperto form a TSV, wherein a Fe⁺²/Fe⁺³ redox system is established in thebath to provide additional copper ions to be electrodeposited bydissolving copper ions from the source of copper metal.
 2. The processof claim 1 wherein the applying is effective to electrodeposit the highpurity copper to completely fill the via.
 3. The process of claim 1wherein the applying is effective to electrodeposit the high puritycopper to form a copper lining in the via of sufficient thickness to becapable of function as a TSV.
 4. The process of claim 1 wherein thedeposited high purity copper is either substantially free of internalstress or includes a level of internal stress that does not result inbending of the silicon substrate upon subsequent processing.
 5. Theprocess of claim 1 wherein the deposited copper is substantially free ofvoids and non-copper inclusions.
 6. The process of claim 1 wherein thebasic metal layer is formed over the barrier layer by one or more of anelectroless plating process, a physical deposition process, a chemicalvapor deposition process, or a plasma-enhanced chemical vapor depositionprocess.
 7. The process of claim 1 wherein the basic metal layer has athickness in the range from about 0.02 microns to about 0.5 microns. 8.The process of claim 1 wherein the basic metal layer comprises copper.9. The process of claim 1 wherein the barrier layer comprises tantalum.10. The process of claim 1 wherein the dielectric layer comprisessilicon dioxide.
 11. The process of any one of claims 110 claim 1wherein in the electrolytic bath, the acid is sulfuric acid at aconcentration in the range from about 50 to about 350 g/l, the source ofcopper ions is copper sulfate pentahydrate at a concentration in therange from about 20 to about 250 g/l, the source of ferrous and/orferric ions is ferrous sulfate heptahydrate and/or ferric sulfatenonahydrate at a concentration in the range from about 1 to about 120g/l, and the at least one additive comprises one or more of a polymericoxygen-containing compound, an organic sulfur compound, a thioureacompound and a polymeric phenazonium compound.
 12. The process of claim1 wherein the electrical voltage is applied in a pulse current or apulse voltage.
 13. The process of claim 12 wherein the electricalvoltage is applied in a reverse pulse form with bipolar pulses includinga forward current pulse and a reverse current pulse.
 14. The process ofclaim 13 wherein the duration of the reverse current pulse is adjustedto about 1 to about 20 milliseconds.
 15. The process of claim 13 whereinthe duration of the forward current pulse is adjusted to about 10 toabout 200 milliseconds.
 16. The process of claim 13 wherein peak currentdensity of the forward current pulse at a work piece surface is adjustedto a maximum of about 15 A/dm².
 17. The process of claim 13 wherein thepeak current density of the reverse current pulse at a work piecesurface is adjusted to a maximum of about 60 A/dm².
 18. The process ofclaim 13 wherein a first current pulse is shifted with respect to asecond current pulse by about 180°.